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Lattice Semiconductor
Table 5-3 lists test application I/Os.
Table 5-3. Counter Registers
Application Support
FPGA Signal Name
col
crs
gtx_clk
mdc
mdio
pc_ack
pc_clk
pc_datain
pc_dataout
pc_error
pc_ready
pc_retry
jtag_present
jtag_parallel
reset_n
rx_clk
rx_dv
rx_er
rxd_0
rxd_1
rxd_2
rxd_3
rxd_4
rxd_5
rxd_6
rxd_7
sys_clk
tx_clk
tx_en
tx_er
txd_0
txd_1
txd_2
txd_3
txd_4
txd_5
txd_6
txd_7
rxmac_clk
txmac_clk
FPGA Pin
Input
Input
Output
Input
Bi-directional
Output
Input
Input
Output
Output
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Notes
Collision detect signal
Carrier sense signal
Tx GMII clock used only in 1 G mode
SMI clock sourced to PHY from FPGA
Bi-directional SMI data to/from PHY from/to MAC
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
Orcastra parallel signals – only valid if jtag_parallel is Low
JTAG is present
Used to select Orcastra interface
1 = JTAG (for HW testing)
0 = Parallel (used during simulation)
Active Low
Rx GMII clock
Rx GMII data valid
Rx GMII error
Rx GMII eata bit 0
Rx GMII data bit 1
Rx GMII data bit 2
Rx GMII data bit 3
Rx GMII data bit 4
Rx GMII data bit 5
Rx GMII data bit 6
Rx GMII data bit 7
Not needed if pkt_loop_clksel is set to 1
Tx GMII clock
Tx GMII enable
Tx GMII error
Tx GMII data bit 0
Tx GMII data bit 1
Tx GMII data bit 2
Tx GMII data bit 3
Tx GMII data bit 4
Tx GMII data bit 5
Tx GMII data bit 6
Tx GMII data bit 7
Rx MAC clock – used internally can be brought out
Tx MAC Clock – used internally can be brought out
IPUG51_03.0, December 2010
56
Tri-Speed Ethernet MAC User’s Guide
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